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AMD Mobile Serial VID Dual-Phase
Fixed-Frequency Controller
Pin Description (continued)
PIN
7
8
9
10
11
12
13
14
15
NAME
TIME
SVC
SVD
THRM
GNDS2
FBDC2
FBAC2
V DDIO
GNDS_NB
FUNCTION
Slew-Rate Adjustment Pin. Connect a resistor R TIME from TIME to GND to set the internal slew rate:
PWM Slew rate = (6.25mV/μs) x (143k Ω / R TIME )
NBV_BUF Slew rate = (7μA) x (143k Ω / R TIME ) / C NBV_BUF
where R TIME is between 35.7k Ω and 357k Ω for corresponding slew rates between 25mV/μs to 2.5mV/μs,
respectively, for the SMPSs, and NBV_BUF currents between 28μA and 2.8μA, respectively, for the
NBV_BUF.
This slew rate applies to both upward and downward VID transitions, and to the transition from boot mode
to VID mode. Downward VID transition slew rate can appear slower because the output transition is not
forced by the SMPS.
The SMPS slew rate for startup and shutdown is fixed at 1mV/μs.
The NBV_BUF slew rate is the same during startup, shutdown, and normal VID transitions.
Serial VID Clock. During the power-up sequence and in debug mode, SVC is the MSB of the 2-bit VID DAC.
Serial VID Data. During the power-up sequence and in debug mode, SVD is the LSB of the 2-bit VID DAC.
Input of Internal Comparator. Connect the output of a resistor- and thermistor-divider (between V CC and
GND) to THRM. Select the components so the voltage at THRM falls below 1.5V (30% of V CC ) at the
desired high temperature.
SMPS2 Remote Ground-Sense Input. Normally connected to GND directly at the load. GNDS2 internally
connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage
drops from the regulator ground to the load ground.
Connect GNDS2 above 0.9V combined-mode operation (unified core). When operating in combined
mode, GNDS1 is used as the remote ground-sense input.
Output of the DC Voltage-Positioning Transconductance Amplifier for SMPS2. Connect a resistor R FBDC2
between FBDC2 and the positive side of the feedback remote sense to set the DC steady-state droop
based on the voltage-positioning gain requirement:
R FBDC2 = R DROOPDC / (R SENSE2 x G m(FBDC2) )
where R DROOPDC is the desired voltage positioning slope and G m(FBDC2) = 1mS typ. R SENSE2 is the
value of the current-sense resistor that is used to provide the (CSP2, CSN2) current-sense voltage.
To disable the load-line, short FBDC2 to the positive remote-sense point.
FBDC2 is high impedance in shutdown.
Output of the AC Voltage-Positioning Transconductance Amplifier for SMPS2. The resistance between
this pin and the positive side of the remote-sensed output voltage sets the transient AC droop:
R FBAC2 = R DROOPAC / (R SENSE2 x G m(FBAC2) )
where R DROOPAC is the transient (AC) voltage-positioning slope that provides an acceptable tradeoff
between stability and load transient response, G m(FBAC2) and R SENSE2 is the value of the current-sense
resistor that is used to provide the (CSP2, CSN2) current-sense voltage.
The maximum difference between transient (AC) droop and DC droop should not exceed ±80mV at the
maximum allowed load current (DC droop is set at the FBDC2 pin).
Internally, V(FBDC2 - GNDS2) goes to the internal voltage integrator (slow DC loop), whereas V(FBAC2 -
GNDS2) goes to the error comparator (fast transient loop).
FBAC2 is high impedance in shutdown.
Note: The AC and DC droop cannot be different by more than ±3mV/A.
CPU I/O Voltage (1.8V or 1.5V). Logic thresholds for SVD and SVC are relative to the voltage at V DDIO .
North Bridge Feedback Remote-Sense Input, Negative Side. Normally connected to GND directly at the
load. GNDS_NB internally connects to a transconductance amplifier that fine tunes the NBV_BUF output
voltage compensating for voltage drops from the regulator ground to the load ground.
16
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